Accelerating Test, Validation and Debug of High Speed Serial by Yongquan Fan PDF

By Yongquan Fan

ISBN-10: 9048193974

ISBN-13: 9789048193974

High-Speed Serial Interface (HSSI) units became frequent in communications, from the embedded to high-performance computing structures, and from on-chip to a large haul. checking out of HSSIs has been a tough subject due to sign integrity concerns, lengthy try time and the necessity of costly tools. Accelerating try out, Validation and Debug of excessive pace Serial Interfaces offers cutting edge try and debug methods and unique directions on tips to arrive to useful try out of contemporary high-speed interfaces.

Accelerating try, Validation and Debug of excessive pace Serial Interfaces first proposes a brand new set of rules that allows us to accomplish receiver attempt greater than one thousand occasions speedier. Then an under-sampling established transmitter attempt scheme is gifted. The scheme can thoroughly extract the transmitter jitter and end the total transmitter try out inside 100ms, whereas the attempt frequently takes seconds. The publication additionally provides and exterior loopback-based checking out scheme, the place and FPGA-based BER tester and a singular jitter injection process are proposed. those schemes might be utilized to validate, try out and debug HSSIs with info cost as much as 12.5Gbps at a reduce try expense than natural ATE options. moreover, the publication introduces an efficieng scheme to enforce excessive functionality Gaussian noise turbines, compatible for comparing BER functionality lower than noise conditions.

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Extra info for Accelerating Test, Validation and Debug of High Speed Serial Interfaces

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According to the receiver characteristics and the test setup, we first propose a jitter tolerance extrapolation algorithm. Based on this algorithm, we then propose acceleration schemes for production test, as well as for characterization and silicon debugging. In this chapter, we first review the operation of a receiver in high-speed serial interfaces, and especially the clock data recovery block, under the influence of jitter, both in- and out-of-band. Then, we show how a jitter tolerance testing is conducted, including a detailed description of the jitter test signal generation.

Because only a single power supply is needed, most digital communication systems, including HSSIs, use this format. 3 Amplitude Noise 33 Figure 2-15 plots the relationship between the BER and the SNR for the above three values of correlation: -1, 0 and 1. Fig. 2-15. BER vs. SNR for baseband transmission If a Gaussian noise at the input of the receiver is the dominant cause of bit errors, according to Equation (2-11) we can get higher BER by reducing the SNR. In simulation or real testing, the SNR can be reduced to a known quantity by adding a controllable amount of noise to the test signal.

Laquai and Cai propose a jitter tolerance test methodology in [40] based on a DDJ injection filter. This approach uses a passive filter that is carefully tuned to condition the data eye seen by the receiver. This filter can add jitter to stress the receiver. Major advantages of the jitter injection filter are that it takes little space on a loadboard and that its cost is very low. However, this methodology does not offer the flexibility of varying the amount of injected jitter. In addition, the amount of the injected jitter is very sensitive to the data rate.

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Accelerating Test, Validation and Debug of High Speed Serial Interfaces by Yongquan Fan


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